From System Architecture to Functional Verification
Core 3
Optimized for Performance, Power and Scalability
Overview
Integrated SoC Design Solution
알파칩스는 고객 요구사항에 최적화된 SoC 설계솔루션을 제공합니다. Architecture 설계부터 RTL Design, Verification, SoC Integration까지 전 과정을 아우르는 전문전인 Engineering 역량을 기반으로 지원하여 안정적인 Silicon 구현을 실현합니다.
ASIC Business Flow
Core Strengths & Capabilities
알파칩스는 전문적인 SoC 설계 경험과 검증된 Methodology를 기반으로 Architecture, RTL Design, Verification, SoC Integration 및 Performance Optimization 전 영역에 걸친 설계 역량을 보규 하고 있습니다.
Advanced SoC Architecture
High-Performance SoC Design
Multi-IP Integration Experience
Protocol Readiness
RTL Design Capability
High-Quality RTL Coding
Reusable & Scalable Design
Verification Methodology
Automotive DFT Support
System-level Validation
Pre-silicon Confidence
SoC Integration
Multi-IP System Orchestration
Bus Architecture Optimization
Connectivity Validation
Performance Optimization
PPA Maximization
Timing-aware Design
Efficient Resource Utilization
Design Service
System Architecture Design Solutions
SoC Architecture 설계부터 RTL Design, Verification, SoC Integration 및 FPGA Validation까지 고객의 개발 환경과 요구사항에 최적화된 End-to-End Design Service를 제공합니다.
System Architecture Design
고객 요구사항을 기반으로 성능, 소비전력, 면적, 대역폭 및 Integration Complexity를 종합적으로 고려하여 최적의 SoC System Architecture를 설계합니다.
Core Capabilities
System Architecture Definition
IP Selection and Configuration
Bus / Interconnect Architecture Design
Performance and Bandwidth Modeling
Power, Clock/Reset and Address Map Planning
RTL Design
SoC System Architecture를 기반으로 Control Logic, Data Path, Interface 및 Low-Power Design을 포함한 고품질의 합성 가능한 RTL을 설계합니다.
Core Capabilities
Microarchitecture and RTL Implementation
Control Logic and FSM Design
Low-power and UPF-aware RTL Design
CDC/RDC-aware Clock and Reset Domain Design
Interface and Data Path Logic Design
Functional Verification
체계적인 Verification Plan을 기반으로 UVM Testbench, Assertion, Coverage 및 Regression을 활용하여 RTL의 기능과 동작을 검증합니다
Core Capabilities
Verification Planning and Test Scenario Definition
UVM Testbench, Sequence and Scoreboard Development
Functional Coverage and Assertion-based Verification
Regression Automation and Coverage Closure
System-Level Verification and Debug
SoC Integration
다양한 IP와 Subsystem을 통합하고 Connectivity, Bus Architecture, Clock/Reset, Power Domain 및 Integration Verification을 통해 안정적인 SoC Top-Level을 구현합니다.
Core Capabilities
SoC Top-level Integration
IP and Subsystem Connectivity
Bus / Interconnect Integration
Clock, Reset and Power Domain Integration
Address Map, Register Map and Integration Verification
Fullchip Top-level Integration & Closure
Hybrid Synthesis Flow: Automated synthesis for productivity, with engineer-driven optimization for timing-critical blocks
FPGA Prototyping & Pre-silicon Validation
SoC 및 Subsystem RTL을 FPGA 기반 Prototype 환경에 구현하고, Pre-silicon Validation을 통해 조기 Bring-up, HW/SW Co-validation 및 System-Level Debugging을 수행합니다.
Core Capabilities
FPGA Prototype Preparation and RTL Porting
HW/SW Co-Validation
System-Level Bring-up and Debugging
Interface and Peripheral Validation
Pre-Silicon Software Bring-up
Design Applications
Supported Applications
알파칩스의 SoC Design & Verification 기술은 AI, Automotive, HPC, Consumer 등 다양한 Application의 SoC 개발에 적용됩니다
