Optimizing Performance, Power and Manufacturability
Core 3
From Netlist to Manufacturing-ready Silicon
Overview
Comprehensive Physical Implementation Solution
알파칩스는 설계 최적화부터 최종 Tape-out까지 Physical Implementation 전 영역의 솔루션을 제공합니다. 검증된 설계 Methodology와 선단 공정 경험을 기반으로 Performance, Power, Area 를 최적화하고 안정적인 Silicon 구현과 성공적인 양산을 지원합니다.
ASIC Business Flow
Core Strengths & Capabilities
다양한 공정과 SoC 개발 경험을 기반으로 복잡한 설계 요구사항에 대응하며, 선단 공정에서도 안정적인 Timing Closure와 설계 품질을 확보할 수 있는 Physical Design 역량을 제공합니다.
Advanced Physical Implementation
Advanced Process Experience
Large-Scale SoC Management
System Optimization
Timing Closure Capability
Advanced STA Methodology
Clock Structure Optimization
Timing Optimization Flow
Multi-corner Multi-mode(MCMM)
Power & Signal Integrity
Stability Verification
Low Power Optimization
Signal Integrity (SI) Optimization
Physical Verification
Foundry Rule Compliance
Layout Validation
Manufacturability Check
Manufacturing Readiness
Final Signoff Flow
GDSII/OASIS Generation
Yield Optimization
Manufacturing Support
Design Service
Physical Design Solutions
Gate-Level Netlist 기반의 Physical Implementation부터 Timing Closure, Power Optimization, Physical Verification 및 Tape-out까지 End-to-End Back-end Design Service를 제공합니다.
Physical Aware Synthesis
Placement, Timing, Power 및 Congestion을 고려한 Synthesis를 통한 Physical Implementation 최적화
Core Capabilities
Floorplan Design
Macro Placement Optimization
Power Grid Planning
IO & Pin Placement
Physical Constraint Definition
Placement, CTS & Routing
Placement, Clock Tree Synthesis 및 Routing을 통한 Timing, Power 및 Congestion 최적화
Core Capabilities
Standard Cell Placement
CTS (Clock Tree Synthesis)
Routing Optimization
Congestion Analysis & Optimization
Physical-aware Optimization
Timing Closure & Signoff STA
다양한 동작 조건에서 Timing Optimization 및 Signoff STA를 통한 목표 성능 및 Timing Closure 확보
Core Capabilities
Static Timing Analysis (STA)
Multi-mode Multi-corner (MMMC) Analysis
Clock Timing Optimization
Setup / Hold Timing Closure
ECO-based Timing Optimization
Power & Signal Integrity
Power Integrity 및 Signal Integrity 분석을 통한 안정적인 Chip 동작 및 신뢰성 확보
Core Capabilities
IR Drop Analysis
Electromigration (EM) Analysis
Crosstalk Analysis
Thermal Analysis
Low Power Optimization
Physical Verification & Signoff
DRC, LVS 등 Physical Verification을 통한 Layout 정확성 및 Foundry 공정 기준 검증
Core Capabilities
DRC Verification
LVS (Layout vs. Schematic) Verification
Antenna Check
Density Verification
Signoff Validation
Tape-out & Manufacturing Support
최종 GDS 준비, Tape-out 및 Foundry Handoff를 통한 안정적인 양산 준비 지원
Core Capabilities
GDSII/OASIS Generation
Final Data Integrity Check
Foundry Interface Support
Tape-out Flow Management
Manufacturing Readiness Review
Design Applications
Supported Applications
다양한 SoC 및 Application에 최적화된 Physical Design을 적용하여 공정, 성능 및 제품별 요구사항에 유연하게 대응합니다.
