IP Solution

Overview

IP Solution

알파칩스는 검증된 IP와 글로벌 파트너 에코시스템을 기반으로 고객의 SoC 개발에 최적화된 IP Solution을 제공합니다.
High-Speed Interface IP, Mixed-Signal Solution, CPU Core 및 Integrated Subsystem까지 다양한 IP Portfolio를 통해
안정적이고 효율적인 SoC 구현을 지원합니다.

Core 1: Maximizing System Value with Proven IP Solutions
Core 2: Advancing SoC Development with IP Subsystems
Core 3: Optimized IP Portfolio for Next-generation Silicon

Solutions Overview

Integrated Subsystem Solutions

검증된 IP와 Integration 기술을 결합하여 복잡한 SoC 설계를 단순화하고 개발 기간을 단축할 수 있는 Integrated Subsystem Solution을 제공합니다.

Built on expertise in Top Integration and Bus Architecture Design for efficient chip-wide data flow.
Plug & Play IPs simplify integration and shorten verification and development cycles.
Integrates diverse IPs, controllers, and interface logic into unified functional units.

Solution

Integrated Subsystem Portfolio

핵심 IP와 Interface를 사전 통합·검증한 Subsystem Portfolio를 통해 SoC Integration의 복잡도를 낮추고 개발 효율성을 향상시킵니다.

Computing Subsystem

Provides an integrated processor subsystem for SoC platforms, including CPU core integration, cache hierarchy configuration, interrupt handling, debug/trace interfaces, and system bus connectivity.

Core Capabilities

CPU Core / Cluster Integration
Cache Hierarchy & Coherency Configuration
Interrupt Controller Integration
Debug & Trace Interface Integration
Compute Subsystem Verification

Memory Subsystem

Provides an integrated memory subsystem for SoC platforms, including DDR/LPDDR controller integration, PHY/DFI interface connectivity, memory access arbitration, and high-bandwidth data path optimization.

Core Capabilities

DDR/LPDDR Controller Integration
DDR PHY / DFI Interface Integration
System Bus Connectivity
Memory Access Arbitration & QoS Optimization
Bandwidth and Latency Optimization
Memory Reliability & Data Integrity Validation

High-Speed I/O Subsystem

Provides an integrated high-speed interface subsystem for SoC platforms, including PCIe controller integration, PHY/PIPE connectivity, DMA data path integration, Root Complex/Endpoint configuration, and interface verification.

Core Capabilities

PCIe Controller and PHY Integration
PHY / PIPE Interface Connectivity
System Bus Bridge and Data Path Integration
Root Complex / Endpoint Configuration
Link Bring-up and Performance Optimization
Protocol and Interface Verification

Global Ecosystem & Strategic Collaboration

Vendor Collaboration & Partners

글로벌 IP Vendor 및 Foundry와의 전략적 파트너십을 기반으로 선단 공정에 최적화된 IP와 안정적인 기술 지원을 제공합니다.

Samsung Foundry
Integration

Samsung Foundry 공정별 특성에 최적화된 설계 환경과 Foundation IP를 기반으로 안정적인 SoC 설계 및 구현을 지원합니다.

Core Capabilities

Standard Cell Libraries: Synthesis 및 GDS Integration에 최적화된 Standard Cell Library 지원
Foundation IP Integration: Logic 및 Memory IP의 Top-Level Integration 지원
I/O Cell Optimization: 안정적인 Interface 구현을 위한 I/O Cell 최적화
Memory Compiler Support: 공정 요구사항에 최적화된 Memory 생성 및 적용 지원
Process-aware Optimization: 공정별 Design Rule 및 Verification 요구사항을 반영한 설계 최적화

Collaboration Strengths

Fast Architecture Proposal: Rapid architecture and system-level planning

Leverages pre-secured IP assets

Optimizes IP combinations for target requirements
Accelerated Time-to-Market: Enables immediate IP integration

Simplifies the development process

Streamlines the complete SoC development cycle